EDA技术实用教程第12章.ppt

EDA 技术实用教程,第 12 章 系统仿真,12.1 仿真,KX康芯科技,仿真也称模拟（Simulation）是对电路设计的一种间接的检测方法，是利用计算机对整个硬件系统进行模拟检测，但却可以不接触具体的硬件系统。,12.2 VHDL源程序仿真,KX康芯科技,图12-1 VHDL仿真流程,12.2 VHDL源程序仿真,KX康芯科技,【例12-1】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY and1 ISPORT(aaa,bbb:IN STD_LOGIC;ccc:OUT STD_LOGIC);END and1;ARCHITECTURE one OF and1 ISBEGINccc=aaa AND bbb;END;,12.2 VHDL源程序仿真,KX康芯科技,【例12-2】LIBRARY IEEE;USE IEEE.std_logic_1164.all;ENTITY TRIBUF_and1 IS GENERIC(ttri:TIME:=1 ns;ttxz:TIME:=1 ns;ttzx:TIME:=1 ns);PORT(in1:IN std_logic;oe:IN std_logic;y:OUT std_logic);END TRIBUF_and1;ARCHITECTURE behavior OF TRIBUF_and1 ISBEGIN PROCESS(in1,oe)BEGIN IF oeEVENT THEN（接下页）,KX康芯科技,IF oe=0 THEN y=TRANSPORT Z AFTER ttxz;ELSIF oe=1 THEN y=TRANSPORT in1 AFTER ttzx;END IF;ELSIF oe=1 THEN y=TRANSPORT in1 AFTER ttri;ELSIF oe=0 THEN y=TRANSPORT Z AFTER ttxz;END IF;END PROCESS;END behavior;LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE work.tribuf_and1;ENTITY and1 IS PORT(aaa:IN std_logic;bbb:IN std_logic;ccc:OUT std_logic);END and1;ARCHITECTURE EPF10K10LC84_a3 OF and1 IS.END EPF10K10LC84_a3;,12.3 仿真激励信号的产生,KX康芯科技,【例12-3】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER4 IS PORT(a,b:IN INTEGER RANGE 0 TO 15;c:OUT INTEGER RANGE 0 TO 15);END ADDER4;ARCHITECTURE one OF ADDER4 ISBEGIN c=a+b;END one;,第一种方法：,12.3 仿真激励信号的产生,KX康芯科技,【例12-4】ENTITY SIGGEN IS PORT(sig1:OUT INTEGER RANGE 0 TO 15;sig2:OUT INTEGER RANGE 0 TO 15);END;ARCHITECTURE Sim OF SIGGEN ISBEGIN sig1=10,5 AFTER 200 ns,8 AFTER 400 ns;sig2=3,4 AFTER 100 ns,6 AFTER 300 ns;END;,12.3 仿真激励信号的产生,KX康芯科技,图12-2 SIGGEN的仿真输出波形,12.3 仿真激励信号的产生,KX康芯科技,【例12-5】ENTITY BENCH ISEND;ARCHITECTURE one OF BENCH IS COMPONENT ADDER4 PORT(a,b:integer range 0 to 15;c:OUT INTEGER RANGE 0 TO 15);END COMPONENT;COMPONENT SIGGEN PORT(sig1:OUT INTEGER RANGE 0 TO 15;sig2:OUT INTEGER RANGE 0 TO 15);END COMPONENT;SIGNAL a,b,c:INTEGER RANGE 0 TO 15;BEGIN U1:ADDER4 PORT MAP(a,b,c);U2:SIGGEN PORT MAP(sig1=a,sig2=b);END;,12.3 仿真激励信号的产生,KX康芯科技,图12-3 BENCH仿真波形图,12.3 仿真激励信号的产生,KX康芯科技,force,-repeat,第二种方法：,force a 0（强制信号的当前值为0）force b 0 0,1 10（强制信号b在时刻0的值为0，在时刻10的值为1）force clk 0 0,1 15 repeat 20（clk为周期信号，周期为20,force a 10 0,5 200,8 400force b 3 0,4 100,6 300,12.4 VHDL测试基准,KX康芯科技,【例12-6】Library IEEE;use IEEE.std_logic_1164.all;entity counter8 is port(CLK，CE，LOAD，DIR，RESET:in STD_LOGIC;DIN:in INTEGER range 0 to 255;COUNT:out INTEGER range 0 to 255);end counter8;architecture counter8_arch of counter8 isbeginprocess(CLK,RESET)variable COUNTER:INTEGER range 0 to 255;begin if RESET=1 then COUNTER:=0;elsif CLK=1 and CLKevent then if LOAD=1 then COUNTER:=DIN;（接下页）,KX康芯科技,Else if CE=1 then if DIR=1 then if COUNTER=255 then COUNTER:=0;Else COUNTER:=COUNTER+1;end if;else if COUNTER=0 then COUNTER:=255;Else COUNTER:=COUNTER-1;end if;end if;end if;end if;end if;COUNT=COUNTER;end process;end counter8_arch;,12.4 VHDL测试基准,KX康芯科技,【例12-7】Entity testbench is end testbench;Architecture testbench_arch of testbench isFile RESULTS:TEXT open WRITE_MODE is results.txt;Component counter8 port(CLK:in STD_LOGIC;RESET:in STD_LOGIC;CE,LOAD,DIR:in STD_LOGIC;DIN:in INTEGER range 0 to 255;COUNT:out INTEGER range 0 to 255);end component;shared variable end_sim:BOOLEAN:=false;signal CLK,RESET,CE,LOAD,DIR:STD_LOGIC;signal DIN:INTEGER range 0 to 255;signal COUNT:INTEGER range 0 to 255;procedure WRITE_RESULTS(CLK，CE，LOAD，LOAD，RESET:STD_LOGIC;（接下页）,KX康芯科技,DIN，COUNT:INTEGER)isVariable V_OUT:LINE;Beginwrite(V_OUT,now,right,16,ps);-输入时间write(V_OUT,CLK,right,2);write(V_OUT,RESET,right,2);write(V_OUT,CE,right,2);write(V_OUT,LOAD,right,2);write(V_OUT,DIR,right,2);write(V_OUT,DIN,right,257);-write outputswrite(V_OUT,COUNT,right,257);writeline(RESULTS,V_OUT);end WRITE_RESULTS;beginUUT:COUNTER8port map(CLK=CLK,RESET=RESET,CE=CE,LOAD=LOAD,DIR=DIR,DIN=DIN,COUNT=COUNT);CLK_IN:processBegin（接下页）,KX康芯科技,if end_sim=false then CLK=0;Wait for 15 ns;CLk=1;Wait for 15 ns;Else Wait;end if;end process;STIMULUS:processBeginRESET=1;CE=1;-计数使能 DIR=1;-加法计数 DIN=250;-输入数据LOAD=0;-禁止加载输入的数据 wait for 15 ns;RESET=0;wait for 1 us;CE=0;-禁止计数脉冲信号进入 wait for 200 ns;CE=1;wait for 200 ns;（接下页）,KX康芯科技,DIR=0;wait for 500 ns;LOAD=1;wait for 60 ns;LOAD=0;wait for 500 ns;DIN=60;DIR=1;LOAD=1;wait for 60 ns;LOAD=0;wait for 1 us;CE=0;wait for 500 ns;CE=1;wait for 500 ns;end_sim:=true;wait;end process;WRITE_TO_FILE:WRITE_RESULTS(CLK,RESET,CE,LOAD,DIR,DIN,COUNT);End testbench_arch;,12.4 VHDL测试基准,KX康芯科技,图12-4 8位计数器测试基准仿真部分波形图,12.5 VHDL系统级仿真,KX康芯科技,图12-5 VHDL系统仿真模型示意图,12.5 VHDL系统级仿真,12.6 使用ModelSim进行仿真,KX康芯科技,12.5 VHDL系统级仿真,【例12-8】LIBRARY ieee;USE ieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;ENTITY cnt4 ISPORT(rst:IN STD_LOGIC;d:IN STD_LOGIC_VECTOR(3 downto 0);load:IN STD_LOGIC;clk,ce:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 downto 0);cout:OUT STD_LOGIC);END cnt4;ARCHITECTURE syn OF cnt4 ISsignal count:std_logic_vector(3 downto 0);BEGIN（接下页）,KX康芯科技,12.5 VHDL系统级仿真,cntproc:process(clk,rst)beginif rst=1 thencount 0);elsif rising_edge(clk)thenif ce=1 thenif load=1 thencount=d;elsecount=count+1;end if;end if;end if;end process;coutproc:process(clk,rst)beginif rst=1 thencout=0;elsif rising_edge(clk)thenif count=1111 thencout=1;elsecout=0;end if;end if;end process;q=count;END syn;,12.6 使用ModelSim进行仿真,KX康芯科技,图12-6 ModelSim的启动界面,12.5 VHDL系统级仿真,12.6 使用ModelSim进行仿真,KX康芯科技,图12-7 建立工程建立项目,12.5 VHDL系统级仿真,12.6 使用ModelSim进行仿真,KX康芯科技,图12-8 开始编译仿真文件,12.5 VHDL系统级仿真,12.6 使用ModelSim进行仿真,KX康芯科技,图12-9 ModelSim编译时的提示信息,12.5 VHDL系统级仿真,12.6 使用ModelSim进行仿真,KX康芯科技,图12-10 装载设计模块,12.5 VHDL系统级仿真,KX康芯科技,图12-11 ModelSim的仿真观察窗,12.5 VHDL系统级仿真,KX康芯科技,12.5 VHDL系统级仿真,【例12-9】library ieee;use ieee.std_logic_1164.all;ENTITY wavegen ISPORT(clk,rst:OUT STD_LOGIC);end wavegen;ARCHITECTURE sim OF wavegen isconstant cycle:Time:=10 ns;BEGINprocess beginclk=0;wait for cycle/2;clk=1;wait for cycle/2;end process;process beginrst=1;wait for cycle*5;rst=0;wait;end process;END sim;,12.6 使用ModelSim进行仿真,KX康芯科技,图12-12 ModelSim的波形观察窗,12.5 VHDL系统级仿真,12.6 使用ModelSim进行仿真,KX康芯科技,图12-12 时钟与复位信号生成,12.5 VHDL系统级仿真,12.7 VHDL的RTL表述,KX康芯科技,12.5 VHDL系统级仿真,12.7.1 行为描述,【例12-10】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;；ENTITY cunter_up ISPORT(reset,clock:IN STD_LOGIC;counter:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END;ARCHITECTURE behv of cunter_up ISSIGNAL cnt_ff:UNSIGNED(7 DOWNTO 0);BEGINPROCESS(clock,reset,cnt_ff)BEGIN IF reset=1 THEN cnt_ff=X00;ELSIF(clock=1 AND clockEVENT)THEN cnt_ff=cnt_ff+1;END IF;END PROCESS;counter=STD_LOGIC_VECTOR(cnt_ff);END ARCHITECTURE behv；,12.7 VHDL的RTL表述,KX康芯科技,12.5 VHDL系统级仿真,12.7.1 行为描述,【例12-11】MODULE counter_up Clock,reset,PIN;Counter7.counter0 PIN ISTYPE COM;Cnt_t_ff0 NODE ISTYPE REG;Counter=counter7.counter0;Cnt=cnt_t_ff0;EQUATIONS Cnt.CLK=clock;Cnt.AR=reset;Cnt:=cnt.FB+1;Counter=cnt;END counter_up,12.7 VHDL的RTL表述,KX康芯科技,12.5 VHDL系统级仿真,12.7.2 数据流描述,12.7.3 结构描述,