[信息与通信]TFT LCD 驱动原理与系统.ppt

TFT LCD 驅動原理與系統,TFT LCD 驅動原理與系統,液晶及液晶顯示器簡介TFT LCD 驅動原理影響TFT LCD 畫面品質的因素TFT LCD Driver ICLCD 數位界面簡介背光板簡介未來趨勢與走向,被動式/主動矩陣式液晶顯示器Passive/Active Matrix LCD,Yelectrode,Xelectrode,Pixel,The Color Pixel of TFT LCD,Color Filter Substrate,TFT Substrate,White Light,Color Light,R,G,B,B,G,R,Clc,Clc,Clc,Arrangement of Color Filter,Stripe,Triangle,Mosaic,Aperture Ratio,a-Si,Drain electrode,Gate electrode,Insulator,Source electrode,n+a-Si,Adjacent gate electrode,Insulator(dielectric substance),Display electrodes,TFT pixel,Effective area:40.7%,Capacitor,TFT LCD 驅動,基本驅動波形極性反轉(polarity inversion)-Frame,row,column,dot電容耦合驅動-二階,三階,四階,Timing Chart of TFT LCDS,Frame Time,Time,Gate,123N,1H,TFTL LCDS Driving Method,Frame N Columns,Frame N+1 Columns,Frame N Columns,Frame N+1 Columns,Column Inversion,Dot Inversion,Frame N Columns,Frame N+1 Columns,Frame N Columns,Frame N+1 Columns,Frame Inversion,Row Inversion,Direct Driving of TFT LCDs,DC Biasof Common,1 Frame/1 Line,GaryScal Voltage,V63V62.V1V0,V0V1.V62V63,Vcom Ac ModulationAddressing of TFT LCDs,1 Frame/1 Line,Common Waveform,GraylevelVoltage,V0,V0,V1,V1,V2,V2,V63,V62,V62,V63,Direct Driving Vs Vcom Modulation,Direct Driving Frame,Row,Column&pixel inversion available Cancel crosstalk&remove flicker：image quality Improve Power dissipation Vcom Modulation Available Frame&Row inversion Poor Power dissipation,影響 LCD 畫面品質的因素,Horizontal CrosstalkVertical CrosstalkShading Crosstalk,液晶電容的效應,液晶電容CLC會隨液晶作用電壓的改變而變化，因此在驅動液晶時會有殘存的DC成份，其所造成的影響Image Sticking.Picture Flicker.液晶作用電壓大時，液晶分子趨向平行電場方向排列液晶作用電場小時，液晶分子趨向垂直電場方向排列,Vp=Vgd Vgd,Cgd Vghl,Cgd+Cs+C,Cgd Vghl,Cgd+Cs+C,Horizontal Line Crosstalk,R,G,B,Csc,Csc,Csc,Color Filter Substrate,B,A,Signal of A Line,Signal of B Line,Common Waveform,Difference of Effective Voltage in B Line,Black Level,Gray Level,Gray Level,Horizontal Area Crosstalk,B,A,Signal of A Line,Signal of B Line,CommonWaveform V1 V2,V1,V2,Difference ofEffective Voltage in B Line,TFT LCD Driver IC,Scan(gate,row)driverData(source,column)driverHigh voltage,mixed modeUsually TCP packageVendors：TI Japan,sharp,NEC,Toshiba,Matsushita,Hitachi,Samsung,LG,vivid,Winbond(cirrus logic,vivid),Mosel(sharp)Maybe in the future,driver IC is not necessary in Large size LCD,The Block Diagram of the TFT LCD Module,TFT-LCDPANEL,CCFL Backlight,Data Driver,Scan Driver,Timing Controller,RGB,CLKHsxVsx,TFT LCD Module,Video Signal Timing Spec.,A,D,E,C,B,Horizontal Display Area,Hs,Total,DisplayArea,O,P,Q,R,S,Vertical Display Area,Vs,TFT-LCD Module,Controller,NO.1,NO.4,256,256,Color TFT-LCD Panel 1280 x 3x 1024,R,G,B,NO.1,NO.9,NO.10,384,384,384,Control Signals(CPV,DI01,V1,V2),GMA0GMA9,Control Signals(CLK,EI01),Display Data 36(6bits x 3x2),Video Signal Timing Spec.,Resolution Vs Outputs-1,Gate Driver No.of Drivers and No.of Output Channels,Channels：120,120/128,150/154,192/200,240,256,Resolution Vs Outputs-2,Source Driver No.of Drivers and No.of Output Channels,Channels：192/240,300/309,384,384/402,Resolution Vs Fmax,解析度愈高，充電時間更短，Driver IC的Fmax也要愈快,Data Driver Key Specifications,Channel numberGray Scale(6bits,8bit)Max Operation Freq.(45MHz,55MHz,65MHz)Pixel Charging Time(eg.R=2K,C=20pF,6.5 s90%,11.5 s 100%)Line or column/dot inversionOutput voltage deviation(10mV,5mV,3mV)Operation voltage Digital：5V,3.3V,2.5V Analog：10V 15VOthers(data inversion,low-power mode,offset canceling,RSDS/LVDS inputetc),Driver IC Trend,240,300/309,384/402,480,65um,40um,50um,4055MHz,65MHz,85MHz,3V/5V,10V/15V,3V/5V/10V,Line Inversion,Dot Inversion,Line/Dot Inversion,6 bit(64 gray scale),8 bit(256 gray scale),2 Level Gate Driver,3 Level Gate Driver,94 95 96 97 98 98 2000,UXGA1600 x 1200,SXGA1280 x 1024,XGA1024 x768,SVGA800 x 600,VGA640 x 480,DisplayResolutionTrend,GrayScaleGrayScaleDrivingMethodOutputVoltageOperationFrequencyTCP ILBPitchOutputChannel,Gate,Data Driver IC Spec,LCD數位界面簡介,類比PC界面簡介LCD數位界面簡介 LVDS TMDS GVIF,Analog Interface&TFT LCD Module,GraphicsController,OSD,ADC,Buffer,Controller,PLL,AnalogRGB,HsVs,DigitalRGB,HsVs,CLKHsxVsx,Timing Controller,Scan Driver,TFT-LCDPANEL,Digital Data Driver,CCFL Backlight,PCACD ModuleTFTLCD Module,Digital Interface&TFT LCD Module,LVDS/PanelLink Rx,DigitalRGB,Clock Hs Vs,Timing Controller,Scan Driver,TFT-LCDPANEL,Digital Data Driver,CCFL Backlight,GraphicsController,LVDS/PanelLink Tx,DigitalRGB,Clock Hs Vs,PC,CABLE,TFT-LCD Module,Digital Interface,High image qualityLong transmission distanceSimple hardwareHigh speed,EMI problemADC/DAC not neededTransmitter/receiver neededMain technologyLVDS,TMDS,GVIFStandardOpenLDI,DFP,DVI,DISM,.,The Digital Interface-LVDS,LVDS interface(TI,NS,Thine)Low voltage differential signalingMainstream in the notebook PC now(close system)7x internal clockPLL range：VGA(20mhz)to XGA(65mhz)Low voltage swings(0.250mv 0.345mv 0.450mv)Reducing EMI&high edge sharpness imageNumber of cable line：4,5,9 pairsLong distance transmission(5m),LVDS,Tx CLK OUTRx CLK IN,Tx OUT 3/Rx IN 3,Tx OUT 2/Rx IN 2,Tx OUT 1/Rx IN 1,Tx OUT 0/Rx IN 0,Previous Cycle,Next Cycle,TxIN5-1 TxIN27-1 TxIN23 TxIN17 TxIN16 TxIN11 TxIN10 TxIN5 TxIN27,TxIN20-1 TxIN19-1 TxIN26 TxIN25 TxIN24 TxIN22 TxIN21 TxIN20 TxIN19,TxIN9-1 TxIN8-1 TxIN18 TxIN15 TxIN14 TxIN13 TxIN12 TxIN9 TxIN8,TxIN1-1 TxIN0-1 TxIN7 TxIN6 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0,FIGURE 16.Parallel TTL Data Inputs Mapped to LVDS Outputs(DS90CR583),LVDS,HostGraphicsController,LCDPanelController,TxCLK IN,RxCLK OUT,Cmos/TTL,Cmos/TTL,FPD LinkDS90CR583,FPD LinkDS90CR584,Data(LVDS),Clock(LVDS),Application,Open LDI,TTL PARALLEL-TO-LVDS,DC BALANCE,DC BALANCE&DESKEW,LVDS-TO-TTL PARALLEL,PLL,8,8,8,8,8,8,8,8,8,8,8,8,RED 1GRN 1BLUE 1RED 2GRN 2BLUE 2,RED 1GRN 1BLUE 1RED 2GRN 2BLUE 2,FPLINEFPFRAMEDRDYControl,FPSHIFT IN 32.5 112MHz(170MHz SPM),CMOS/TTL Inputs,DS90C387,DS90C387,PLL,LVDS DATA 195 672 Mbps per channel,LVDS CLOCK(32.5 to 112MHz),5.376Gbps,FPLINEFPFRAMEDRDYControl,FPSHIFT OUT 32.5 112MHz,CMOS/TTL Inputs,The Digital Interface-TMDS,PanelLink interface(silicon image)Transition minimized differential signalingAdopted by the LCD monitor interface(open system),And determine the correct sampling point.10 x internal clock&voltage swing=400 to 600 mVOnly 4 twisted pairs,support VGA to UXGA3 times Oversampling the serial data streamCode is encoded to provide DC balancingLong distance transmission easy(5m)Data-to-data skew tolerance 1 clock cycle,TMDS,TMDS(Transition Minimized Differential Signaling)is an interface standard based on PanelLink Technology developed by Silicon Image,Inc.,SwingControl,Encoder/Serialized,PLL,GraphicController,TerminationControl,Recovery/Decorder/Desirializer,PLL,LCDPanel,Data,Data,DE,DE,Controls,Controls,Clock,Clock,TX1(Green),TX0(Blue),TX2(Red),Clock,24,5,24/36,5,VCC,VCC,ParallelData(CMOS),ParallelData(CMOS),TMDS I/F,Host,Monitor,Block Diagram of TNDS,DVI,DVI(digital visual interface)Promoted by DDWGIntel,IBM,HP,Compaq,NEC,Fujitsu,silicon imageDual channel TMDSSupport VGA to QXGAPixel clock：25mhz 330mhz,DVI,DVI:Molex 24+5 pin connector pin assignment,Pin 1,Pin 24,Pin 8,Pin 17,C1 C2,C4,GVIF,GVIF(gigabit video interface)Promoted by SONYAllows using small connector and long cable(10m)Only one pair differential signal usedSupport 24bit/pixel,XGAPixel clock：25mhz 65mhz400mv voltage swingDC balancingUsing 2pair,support to SXGA,Conclusion,Interface transits from analog to digitalCost dominate transition timeNotebook LVDSLCD monitor,PC graphics card DVIEMC is still a big issueHigh resolution is digitals world!,