数字逻辑设计及应用17课件.ppt
Chapter 7 Sequential Logic Design Principles( 时序逻辑设计原理 ),Latches and Flip-Flops (锁存器和触发器 ) Clocked Synchronous State-Machine Analysis (同步时序分析) Clocked Synchronous State-Machine Design (同步时序设计),Digital Logic Design and Application (数字逻辑设计及应用),1,Chapter 7 Sequential Logic Des,Introduction,Combinational circuitOutputs depend solely on the present combination of the circuit inputs values,Vs. sequential circuit: Has “memory” that impacts outputs too,2,IntroductionCombinational circ,Basic Concepts (基本概念),Logic Circuits are Classified into Two Types (逻辑电路分为两大类)：Combinational Logic Circuit （组合逻辑电路）Sequential Logic Circuit （时序逻辑电路）,Digital Logic Design and Application (数字逻辑设计及应用),3,Basic Concepts (基本概念)Logic Cir,Basic Concepts (基本概念),Combinational Logic Circuit （组合逻辑电路）,Outputs Depend Only on its Current Inputs.(任何时刻的输出仅取决与当时的输入),Character of Circuit: No Feedback Circuit, No Memory Device(电路特点：无反馈回路、无记忆元件),Digital Logic Design and Application (数字逻辑设计及应用),4,Basic Concepts (基本概念)Combinati,Basic Concepts (基本概念),Sequential Logic Circuit （时序逻辑电路）,Outputs Depend Not Only on its Current Inputs, But also on the Past Sequence of Inputs.(任一时刻的输出不仅取决与当时的输入，还取决于过去的输入序列),Character of Circuit: Have Feedback Circuit, Have Memory Device(电路特点：有反馈回路、有记忆元件),Digital Logic Design and Application (数字逻辑设计及应用),5,Basic Concepts (基本概念)Sequentia,Basic Concepts (基本概念),Sequential Logic Circuit （时序逻辑电路）,Finite-State Machine: Have Finite States.(有限状态机：有有限个状态。）,A Clock Signal is Active High if state changes occur at the clock Rising Edge or when the clock is High, and Active Low in the complementary case.(时钟信号高电平有效是指在时钟信号的上升沿或时钟的高电平期间发生变化。）,Digital Logic Design and Application (数字逻辑设计及应用),6,Basic Concepts (基本概念)Sequentia,Basic Concepts (基本概念),Sequential Logic Circuit （时序逻辑电路）,Clock Period: The Time between Successive transitions in the same direction.(时钟周期：两次连续同向转换之间的时间。）,Clock Frequency: The Reciprocal of the Clock Period(时钟频率：时钟周期的倒数。）,Digital Logic Design and Application (数字逻辑设计及应用),Figure 7-1,7,Basic Concepts (基本概念)Sequentia,Basic Concepts (基本概念),Sequential Logic Circuit （时序逻辑电路）,Clock Tick: The First Edge of Pulse in a clock period or sometimes the period itself.(时钟触发沿：时钟周期内的第一个脉冲边沿，或时钟本身。）,Duty Cycle: The Percentage of time that the clock signal is at its asserted level. (占空比：时钟信号有效时间与时钟周期的百分比。）,Digital Logic Design and Application (数字逻辑设计及应用),Figure 7-1,8,Basic Concepts (基本概念)Sequentia,思考：能否只用一片1位全加器进行串行加法？,X YCI COS,反馈,利用反馈和时钟控制,Digital Logic Design and Application (数字逻辑设计及应用),9,思考：能否只用一片1位C1S0X0 Y0C0X,暂存,时钟控制,需要具有记忆功能的逻辑单元，能够暂存运算结果。,利用反馈和时钟控制,Digital Logic Design and Application (数字逻辑设计及应用),10,暂存X YCi+1SiXi YiCiX,7.1 Bistable Elements (双稳态元件),1,1,0,0,It has Two Stable State: Q = 1 ( HIGH ) and Q = 0 ( LOW ) (电路有两种稳定状态：Q = 1 ( 1态 ) 和 Q = 0 ( 0态 ) Bistable Circuit（双稳电路）,0,0,1,1,Digital Logic Design and Application (数字逻辑设计及应用),11,7.1 Bistable Elements (双稳态元件),7.1 Bistable Elements (双稳态元件),1,1,0,0,When Power is first Applied to the circuit, it Randomly Comes up in One State or the Other and Stays there Forever. ( 只要一接电源，电路就随机出现两种状态中的一种，并永久地保持这一状态。),0,0,1,1,Digital Logic Design and Application (数字逻辑设计及应用),12,7.1 Bistable Elements (双稳态元件),Digital Logic Design and Application (数字逻辑设计及应用),13,Vin1Vout1Vin2Vout2Vout2Vin2= V,Metastable Behavior(亚稳态特性),Random Noise will tend to Drive a circuit that is Operating at the Metastable Point toward one of the Stable operating point.( 随机噪声会驱动工作于亚稳态点的电路转移到一个稳态的工作点上去 ),Digital Logic Design and Application (数字逻辑设计及应用),14,Metastable Behavior(亚稳态特性)Ran,所有的时序电路对亚稳态都是敏感的,Metastable Behavior(亚稳态特性),亚稳态,Apply a definite Pulse Width from a Stable state to the Other.(从一个“稳态”转换到另一个“稳态”需加一定宽度的脉冲（足够的驱动）),Digital Logic Design and Application (数字逻辑设计及应用),15,所有的时序电路对亚稳态都是敏感的Metastable Beh,7.2 Latches and Flip-Flops(锁存器与触发器), The Basic Building Blocks of most Sequential Circuits.(大多数时序电路的基本构件)Latches（锁存器）根据输入，直接改变其输出（无使能端）有使能端时，在使能信号的有效电平之内都可根据输入直接改变其输出状态,Digital Logic Design and Application (数字逻辑设计及应用),16,7.2 Latches and Flip-Flops(锁,7.2 Latches and Flip-Flops(锁存器与触发器), The Basic Building Blocks of most Sequential Circuits.(大多数时序电路的基本构件)Flip-Flops（ F/F,触发器）只在时钟信号的有效边沿改变其输出状态,Digital Logic Design and Application (数字逻辑设计及应用),17,7.2 Latches and Flip-Flops(锁,S-R Latch (S-R锁存器)S-R Latch with Enable (具有使能端的S-R锁存器)D Latch (D锁存器)Edge-Triggered D Flip-Flops (边沿触发式D触发器)Edge-Triggered D Flip-Flops with Enable (具有使能端的边沿触发式D触发器),Digital Logic Design and Application (数字逻辑设计及应用),7.2 Latches and Flip-Flops(锁存器与触发器),18,S-R Latch (S-R锁存器)Digital Logi,Scan Flip-Flops (扫描触发器)Master/Slave Flip-Flops (S-R、J-K） (主从式触发器)Edge-Triggered J-K Flip-Flops (边沿触发式J-K触发器)T Flip-Flop (T触发器),Digital Logic Design and Application (数字逻辑设计及应用),7.2 Latches and Flip-Flops(锁存器与触发器),19,Scan Flip-Flops Digital Logic,S-R Latches (S-R锁存器),（1）S = R = 0,电路维持原态,工作原理：,Qn+1 = Qn QLn+1 = QLn,新态,原态,Digital Logic Design and Application (数字逻辑设计及应用),20,S-R Latches (S-R锁存器)QQLRS（1）S,工作原理：,（2）S = 0, R = 1,a. 原态：Qn=0，QLn=1,0,1,新态：Qn+1=0，QLn+1=1,b. 原态：Qn=1，QLn=0,新态：Qn+1=0，QLn+1=1,锁存器清0：Qn+1=0 QLn+1=1,即使S,R无效（=0）锁存器仍能锁定0态,Reset,1,0,1,Digital Logic Design and Application (数字逻辑设计及应用),S-R Latches (S-R锁存器),21,QQLRS工作原理：10（2）S = 0, R = 1a.,工作原理：,（3）S = 1, R = 0,a. 原态：Qn=1，QLn=0,1,0,新态：Qn+1=1，QLn+1=0,b. 原态：Qn=0，QLn=1,新态：Qn+1=1，QLn+1=0,锁存器置1：Qn+1=1 QLn+1=0,即使S,R无效（=0）锁存器仍能锁定1态,Set,1,1,0,Digital Logic Design and Application (数字逻辑设计及应用),S-R Latches (S-R锁存器),22,QQLRS工作原理：01（3）S = 1, R = 0a.,工作原理：,（3）S = R = 1,Qn+1 = QLn+1 = 0,当S,R无效（=0）时，,亚稳态，对噪声敏感状态不确定,“禁止”,Digital Logic Design and Application (数字逻辑设计及应用),S-R Latches (S-R锁存器),23,QQLRS工作原理：（3）S = R = 100Qn+1 =,Digital Logic Design and Application (数字逻辑设计及应用),S-R Latches (S-R锁存器),Logic Symbol,Function Table,24,S Q(逻辑符号)S Q(逻辑符号),状态图,Qn+1 = S + RQn,SR = 0,约束条件,S=1,R=0,S=0,R=1,S=XR=0,S=0R=X,Digital Logic Design and Application (数字逻辑设计及应用),25,状态图0001110 00 01 11,Q,tpLH(SQ),tpHL(RQ),传播延迟,最小脉冲宽度,Digital Logic Design and Application (数字逻辑设计及应用),Figure 7-8,26,tpw(min)0 0S R维持原态Q QLSRQt,S-R锁存器的动作特点,输入信号在全部有效电平内，都能直接改变锁存器的状态（直接置位复位触发器）输入端需遵守约束条件抗干扰能力最低当S=R=1，然后同时取消时S和R端输入信号脉冲宽度过小S和R端输入信号同时取反,Digital Logic Design and Application (数字逻辑设计及应用),27,S-R锁存器的动作特点输入信号在全部有效电平内，都能直接改变,第7章作业,7.4(7.2)7.5(7.3)7.7(7.5)7.12(7.9) 7.13(7.10)7.16(7.13)7.17(7.14)7.18(7.15)7.19(7.16),7.20(7.19)7.21(7.20)(c) 7.41(7.27)7.43(7.28)7.46(7.34)7.51(7.47)7.52(7.49)7.77(7.68),28,第7章作业7.4(7.2)7.20(7.19)28,Draw the Output Waveform of the S-R Latch,Digital Logic Design and Application (数字逻辑设计及应用),A Class Problem ( 每课一题 ),S,R,Q,29,Draw the Output Waveform of th,
